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Ivy Bridge-E

Ivy Bridge
Ivy Bridge Codename Logo.jpg
Intel's internally used Ivy Bridge logo
CPUID code 0306A9h
Product code 80637 (desktop)
L1 cache 64 KB per core
L2 cache 256 KB per core
L3 cache MB to 8 MB shared
Model Pentium G Series
Created 29 April 2012
Transistors 2,104 M 22 nm (Tri-Gate)
Architecture Sandy Bridge x86
Instructions MMX, AES-NI, CLMUL
Extensions
Socket(s)
Predecessor Sandy Bridge (Tock)
Successor Haswell (Tock/Architecture)
GPU HD Graphics 2500
650 MHz to 1150 MHz
HD Graphics 4000
350 MHz to 1300 MHz
HD Graphics P4000
650 MHz to 1250 MHz
Ivy Bridge-E
CPUID code 0306Exh
Product code 80633
L1 cache 32 KB per core
L2 cache 256 KB per core
L3 cache 15 MB shared
Model Core i7-49xx Series
Created 10 September 2013
Transistors 1.86B 22 nm (S1)
Architecture Sandy Bridge x86
Instructions MMX, AES-NI, CLMUL
Extensions
Socket(s)
Predecessor Sandy Bridge-E
Successor Haswell-E
Ivy Bridge-EN
CPUID code 0306Exh
Product code 80634
L1 cache 32 KB per core
L2 cache 256 KB per core
L3 cache 10 MB to 25 MB shared
Model Xeon E5-x4xx v2 Series
Created 10 September 2013
Transistors 1.86B 22 nm (S1)
Architecture Sandy Bridge x86
Instructions MMX, AES-NI, CLMUL
Extensions
Socket(s)
Predecessor Sandy Bridge-EN
Successor Haswell-EN
Ivy Bridge-EP
CPUID code 0306Exh
Product code 80635
L1 cache 32 KB per core
L2 cache 256 KB per core
L3 cache 10 MB to 30 MB shared
Model Xeon E5-x6xx v2 Series
Created September 10, 2013
Transistors 1.86B 22 nm (S1)
Architecture Sandy Bridge x86
Instructions MMX, AES-NI, CLMUL
Extensions
Socket(s)
Predecessor Sandy Bridge-EP
Successor Haswell-EP
Ivy Bridge-EX
CPUID code 0306Exh
Product code 80636
L1 cache 32 KB per core
L2 cache 256 KB per core
L3 cache 12 MB to 37.5 MB shared
Model Xeon E7-x8xx v2 Series
Created Q1, 2014
Transistors 4.3B 22 nm (S1)
Architecture Sandy Bridge x86
Instructions MMX, AES-NI, CLMUL
Extensions
Socket(s)
Predecessor Westmere-EX
Successor Haswell-EX

Ivy Bridge is the codename for a "third generation" line of processors based on the 22 nm manufacturing process developed by Intel. The name is also applied more broadly to the 22 nm die shrink of the Sandy Bridge microarchitecture based on FinFET ("3D") tri-gate transistors, which is also used in the Xeon and Core i7 Ivy Bridge-EX (Ivytown), Ivy Bridge-EP and Ivy Bridge-E microprocessors released in 2013.

Ivy Bridge processors are backwards compatible with the Sandy Bridge platform, but such systems might require a firmware update (vendor specific). In 2011, Intel released the 7-series Panther Point chipsets with integrated USB 3.0 to complement Ivy Bridge.

Volume production of Ivy Bridge chips began in the third quarter of 2011.Quad-core and dual-core-mobile models launched on 29 April 2012 and 31 May 2012 respectively. Core i3 desktop processors, as well as the first 22 nm Pentium, were announced and available the first week of September, 2012.

The Ivy Bridge CPU microarchitecture is a shrink from Sandy Bridge and remains largely unchanged. Like its predecessor, Sandy Bridge, Ivy Bridge was also primarily developed by Intel's Israel branch, located in Haifa, Israel. Notable improvements include:

The mobile and desktop Ivy Bridge chips also include significant changes over Sandy Bridge:

Compared to its predecessor, Sandy Bridge:

Ivy Bridge's temperatures are reportedly 10 °C higher compared to Sandy Bridge when a CPU is overclocked, even at default voltage setting. Impress PC Watch, a Japanese website, performed experiments that confirmed earlier speculations that this is because Intel used a poor quality (and perhaps lower cost) thermal interface material (thermal paste, or "TIM") between the chip and the heat spreader, instead of the fluxless solder of previous generations. The mobile Ivy Bridge processors are not affected by this issue because they do not use a heat spreader between the chip and cooling system.


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