22 nanometer

The 22 nanometer (22 nm) node is the process step following the 32 nm in CMOS semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22 nm. It was first introduced by semiconductor companies in 2008 for use in memory products, while first consumer-level CPU deliveries started in April 2012.

The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm (about twice the diameter of a silicon atom), which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point, possibly disturbing Moore's law.

The 22 nm process was superseded by commercial 14 nm technology in 2014.

On August 18, 2008, AMD, Freescale, IBM, STMicroelectronics, Toshiba, and the College of Nanoscale Science and Engineering (CNSE) announced that they jointly developed and manufactured a 22 nm SRAM cell, built on a traditional six-transistor design on a 300 mm wafer, which had a memory cell size of just 0.1 μm². The cell was printed using immersion lithography.

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