Sandy Bridge (CPU)
| Max. CPU clock rate | 1.60 GHz to 3.60 GHz |
|---|---|
| Product code | 80623 (desktop) |
| L1 cache | 64 KB per core |
| L2 cache | 256 KB per core |
| L3 cache | 1 MB to 8 MB shared 10 MB to 15 MB (Extreme) 3 MB to 20 MB (Xeon) |
| Model | Celeron Series Pentium Series Core i3/i5/i7/i7 Extreme Series Xeon E3/E5 Series |
| Created | January 2011 |
| Transistors | 504 M 32nm (Q0) |
| Architecture | Sandy Bridge x86 |
| Instructions | MMX, AES-NI, CLMUL |
| Extensions | |
| Socket(s) | |
| Predecessor | Westmere (Tick) |
| Successor | Ivy Bridge (Tick) |
| GPU |
HD Graphics 650 MHz to 1100 MHz HD Graphics 2000 650 MHz to 1250 MHz HD Graphics 3000 650 MHz to 1350 MHz HD Graphics P3000 850 MHz to 1350 MHz |
Sandy Bridge is the codename for a microarchitecture developed by Intel beginning in 2005 for central processing units in computers to replace the Nehalem microarchitecture. Intel demonstrated a Sandy Bridge processor in 2009, and released first products based on the architecture in January 2011 under the Core brand. Developed primarily by the Israeli branch of Intel, the codename was originally "Gesher" (meaning "bridge" in Hebrew).
Sandy Bridge implementations targeted a 32 nanometer manufacturing process, while Intel's subsequent product, codenamed Ivy Bridge, uses a 22 nanometer process. The Ivy Bridge die shrink, known in the model as the "tick", is based on FinFET (non-planar, "3D") tri-gate transistors. Intel demonstrated the Ivy Bridge processors in 2011.
A Core i7 2600 Sandy Bridge CPU at 3.4 GHz with 1333MHz DDR3 memory reaches 83 GFLOPS performance in the Whetstone benchmark and 118,000 MIPS in the Dhrystone benchmark.
Developed primarily by the Israel branch of Intel, the codename was originally "Gesher" (meaning "bridge" in Hebrew). The name was changed to avoid being associated with the defunct Gesher political party; the decision was led by Ron Friedman, vice president of Intel managing the group at the time. Intel demonstrated a Sandy Bridge processor with A1 stepping at 2 GHz during the Intel Developer Forum in September 2009.
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