Intel Itanium
Itanium 2 processor
|
|
| Produced | From mid-2001 to present |
|---|---|
| Common manufacturer(s) |
|
| Max. CPU clock rate | 733 MHz to 2.66 GHz |
| FSB speeds | 300 MHz to 667 MHz |
| Instruction set | Itanium |
| Cores | 1, 2, 4 or 8 |
Itanium processor
|
|
| Produced | From June 2001 to June 2002 |
|---|---|
| Common manufacturer(s) |
|
| Max. CPU clock rate | 733 MHz to 800 MHz |
| FSB speeds | 266 MT/s |
| Instruction set | Itanium |
| Cores | 1 |
| L2 cache | 96 KB |
| L3 cache | 2 or 4 MB |
| Socket(s) |
|
| Core name(s) |
|
|
Itanium 2 processor
|
|
| Produced | From 2002 to 2010 |
|---|---|
| Designed by | Intel |
| Common manufacturer(s) |
|
| Max. CPU clock rate | 900 MHz to 2.53 GHz |
| Instruction set | Itanium |
| Cores | 1, 2, 4 or 8 |
| L2 cache | 256 KB on Itanium2 256 KB (D) + 1 MB(I) or 512 KB (I) on (Itanium2 9x00 series) |
| L3 cache | 1.5-32 MB |
| Socket(s) |
|
| Core name(s) |
|
Itanium (/aɪˈteɪniəm/ eye-TAY-nee-əm) is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). Intel markets the processors for enterprise servers and high-performance computing systems. The Itanium architecture originated at Hewlett-Packard (HP), and was later jointly developed by HP and Intel.
Itanium-based systems have been produced by HP (the HP Integrity Servers line) and several other manufacturers. In 2008, Itanium was the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, Power Architecture, and SPARC.
In February 2017, Intel began releasing the current generation, Kittson, to test customers; in May 2017, it began shipping in volume. Intel has announced that it is the last processor, with no successor developed.
In 1989, HP determined that Reduced Instruction Set Computing (RISC) architectures were approaching a processing limit at one instruction per cycle. HP researchers investigated a new architecture, later named Explicitly Parallel Instruction Computing (EPIC), that allows the processor to execute multiple instructions in each clock cycle. EPIC implements a form of very long instruction word (VLIW) architecture, in which a single instruction word contains multiple instructions. With EPIC, the compiler determines in advance which instructions can be executed at the same time, so the microprocessor simply executes the instructions and does not need elaborate mechanisms to determine which instructions to execute in parallel. The goal of this approach is twofold: to enable deeper inspection of the code at compile time to identify additional opportunities for parallel execution, and to simplify processor design and reduce energy consumption by eliminating the need for runtime scheduling circuitry.
...
Wikipedia