IA-64

Itanium (Merced)

Itanium processor
Produced	From June 2001 to June 2002
Common manufacturer(s)	Intel
Max. CPU clock rate	733 MHz to 800 MHz
FSB speeds	266 MT/s
Instruction set	Itanium
Cores	1
L2 cache	96 KB
L3 cache	2 or 4 MB
Socket(s)	PAC418
Core name(s)	Merced

Itanium 2 (McKinley)

Itanium 2 processor
Produced	From 2002 to 2010
Designed by	Intel
Common manufacturer(s)	Intel
Max. CPU clock rate	900 MHz to 2.53 GHz
Instruction set	Itanium
Cores	1, 2, 4 or 8
L2 cache	256 KB on Itanium2 256 KB (D) + 1 MB(I) or 512 KB (I) on (Itanium2 9x00 series)
L3 cache	1.5-32 MB
Socket(s)	PAC611 FC-LGA6 (LGA1248) (Itanium 9300 series)
Core name(s)	McKinley Madison Hondo Deerfield Montecito Montvale Tukwila Poulson

IA-64 (also called Intel Itanium architecture) is the instruction set architecture (ISA) of the Itanium family of 64-bit Intel microprocessors. The basic ISA specification originated at Hewlett-Packard (HP), and was evolved and then implemented in a new processor microarchitecture by Intel with HP's continued partnership and expertise on the underlying EPIC design concepts. In order to establish what was their first new ISA in 20 years and bring an entirely new product line to market, Intel made a massive investment in product definition, design, software development tools, OS, software industry partnerships, and marketing. To support this effort Intel created the largest design team in their history and a new marketing and industry enabling team completely separate from x86. The first Itanium processor, codenamed Merced, was released in 2001.

The Itanium architecture is based on explicit instruction-level parallelism, in which the compiler decides which instructions to execute in parallel. This contrasts with other superscalar architectures, which depend on the processor to manage instruction dependencies at runtime. In all Itanium models, up to and including Tukwila, cores execute up to six instructions per clock cycle.

As of 2008^[update], Itanium was the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, Power Architecture, and SPARC.

In 1989, HP began to become concerned that reduced instruction set computing (RISC) architectures were approaching a processing limit at one instruction per cycle. Both Intel and HP researchers had been exploring computer architecture options for future designs and separately began investigating a new concept known as very long instruction word (VLIW) which came out of research by Yale University in the early 1980s. VLIW is a computer architecture concept (like RISC and CISC) where a single instruction word contains multiple instructions encoded in one very long instruction word to facilitate the processor to executing multiple instructions in each clock cycle. Typical VLIW implementations rely heavily on sophisticated compilers to determine at compile time which instructions can be executed at the same time and the proper scheduling of these instructions for execution and also to help predict the direction of branch operations. The value of this approach is to do more useful work in fewer clock cycles and to simplify processor instruction scheduling and branch prediction hardware requirements theoretically reducing processor complexity and cost and reducing energy consumption.