Power Architecture

Power Architecture

Designer	Power.org
Bits	32-bit/64-bit (32 → 64)
Introduced	2006
Version	2.07
Design	RISC
Type	Register-Register
Encoding	Fixed/Variable
Branching	Condition code
Endianness	Big/Bi
Extensions	AltiVec, APU, DSP, CBEA
Open	Yes
Registers
32× 64/32-bit general purpose registers 32× 64-bit floating point registers 32× 128-bit vector registers 32-bit condition code register 32-bit link register 32-bit count register + more

Power Architecture is a registered trademark for similar reduced instruction set computing (RISC) instruction sets for microprocessors developed and manufactured by such companies as IBM, Freescale, AppliedMicro, LSI, e2v and Synopsys. The governing body is Power.org, comprising over 40 companies and organizations.

"Power Architecture" is a broad term including all products based on newer POWER, PowerPC and Cell processors. The term "Power Architecture" should not be confused with IBM's different generations of "POWER Instruction Set Architecture", an earlier instruction set for IBM RISC processors of the 1990s from which the PowerPC instruction set was derived.

Power Architecture is a family name describing processor architecture, software, toolchain, community and end-user appliances and not a strict term describing specific products or technologies.

There can be misunderstanding of the meaning of the terms, POWER, PowerPC and Power Architecture. The following glossary gives brief descriptions of each term, along with links to articles with details.

Main articles: POWER processors, POWER1, POWER2, POWER3, POWER4, POWER5, POWER6, POWER7, POWER8 and POWER9

...
Wikipedia