POWER5
| Produced | 2004 |
|---|---|
| Designed by | IBM |
| Max. CPU clock rate | 1.5 GHz to 2.3 GHz |
| Min. feature size | 130 nm to 90 nm |
| Instruction set | Power Architecture (PowerPC v.2.02) |
| Cores | 2 |
| L1 cache | 32+32 KB/core |
| L2 cache | 1.875 MB/chip |
| L3 cache | 36 MB/chip (off-chip) |
| Predecessor | POWER4 |
| Successor | POWER6 |
The POWER5 is a microprocessor developed and fabricated by IBM. It is an improved version of the POWER4. The principal improvements are support for simultaneous multithreading (SMT) and an on-die memory controller. The POWER5 is a dual-core microprocessor, with each core supporting one physical thread and two logical threads, for a total of two physical threads and four logical threads.
Technical details of the microprocessor were first presented at the 2003 Hot Chips conference. A more complete description was given at Microprocessor Forum 2003 on 14 October 2003. The POWER5 was not sold openly and was used exclusively by IBM and their partners. Systems using the microprocessor were introduced in 2004. The POWER5 competed in the high-end enterprise server market, mostly against the Intel Itanium 2 and to a lesser extent, the Sun Microsystems UltraSPARC IV and the Fujitsu SPARC64 V. It was superseded in 2005 by an improved iteration, the POWER5+.
The POWER5 is a further development of the POWER4. The addition of two-way multithreading required the duplication of the return stack, program counter, instruction buffer, group completion unit and store queue so that each thread may have its own. Most resources, such as the register files and execution units, are shared, although each thread sees its own set of registers. The POWER5 implements simultaneous multithreading (SMT), where two threads are executed simultaneously. The POWER5 can disable SMT to optimize for the current workload.
As many resources such as the register files are shared by two threads, they are increased in capacity in many cases to compensate for the loss of performance. The number of integer and floating-point registers is increased to 120 each, from 80 integer and 72 floating-point registers in the POWER4. The floating-point instruction cache is also increased in capacity to 24 entries from 20. The capacity of the L2 unified cache was increased to 1.875 MB and the set-associativity to 10-way. The unified L3 cache was brought on-package instead of located externally in separate chips. Its capacity was increased to 36 MB. Like the POWER4, the cache is shared by the two cores. The cache is accessed via two unidirectional 128-bit buses operating at half the core frequency.
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