POWER8
| Produced | 2013 |
|---|---|
| Designed by | IBM |
| Max. CPU clock rate | 2.5 GHz to 5 GHz |
| Min. feature size | 22 nm |
| Instruction set | Power Architecture (Power ISA v.2.07) |
| Cores | 4, 6, 8, 10 or 12 |
| L1 cache | 64+32 KB per core |
| L2 cache | 512 KB per core |
| L3 cache | 8 MB per chiplet |
| L4 cache | 16 MB per Centaur |
| Predecessor | POWER7 |
| Successor | POWER9 |
POWER8 is a family of superscalar symmetric multiprocessors based on the Power Architecture, and introduced in August 2013 at the Hot Chips conference. The designs are available for licensing under the OpenPOWER Foundation, which is the first time for such availability of IBM's highest-end processors.
Systems based on POWER8 became available from IBM in June 2014. According to Ken King at IBM, systems and POWER8 processor designs made by other OpenPOWER members will be available in early 2015, but Tyan seems to be ready to ship earlier than that, in October 2014.
POWER8 is designed to be a massively multithreaded chip, with each of its cores capable of handling eight hardware threads simultaneously, for a total of 96 threads executed simultaneously on a 12-core chip. The processor makes use of very large amounts of on- and off-chip eDRAM caches, and on-chip memory controllers enable very high bandwidth to memory and system I/O. For most workloads, the chip is said to perform two to three times as fast as its predecessor, the POWER7.
POWER8 comes in 4-, 6-, 8-, 10- and 12-core variants; each version is fabricated in a 22 nm silicon on insulator (SOI) process using 15 metal layers. The 12-core version consists of 4.2 billion transistors and is 650 mm2 large while the 6-core version is only 362 mm2 large.
Where previous POWER processors use the GX++ bus for external communication, POWER8 removes this from the design and replaces it with the CAPI port (Coherent Accelerator Processor Interface) that is layered on top of PCI Express 3.0. The CAPI port is used to connect auxiliary specialized processors such as GPUs, ASICs and FPGAs. Units attached to the CAPI bus can use the same memory address space as the CPU, thereby reducing the computing path length. At the 2013 ACM/IEEE Supercomputing Conference, IBM and Nvidia announced an engineering partnership to closely couple POWER8 with Nvidia GPUs in future HPC systems, with the first of them announced as the Power Systems S824L.
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