IBM z196
| Produced | 2010 |
|---|---|
| Designed by | IBM |
| Max. CPU clock rate | 3.8 GHz to 5.2 GHz |
| Min. feature size | 45 nm |
| Instruction set | z/Architecture (ARCHLVL 3) |
| Cores | 4 |
| L1 cache | 64+128 KB/core |
| L2 cache | 1.5 MB/core |
| L3 cache | 24 MB/chip |
| Predecessor | z10 |
| Successor | zEC12 |
The z196 microprocessor is a chip made by IBM for their zEnterprise 196 mainframe computers, announced on July 22, 2010. The processor was developed over a three-year time span by IBM engineers from Poughkeepsie, New York; Austin, Texas; and Böblingen, Germany at a cost of US$1.5 billion. Manufactured at IBM's Fishkill, New York fabrication plant, the processor began shipping on September 10, 2010. IBM stated that it was the world's fastest microprocessor at the time.
The chip measures 512.3 mm2 and consists of 1.4 billion transistors fabricated in IBM's 45 nm CMOS silicon on insulator fabrication process, supporting speeds of 5.2 GHz: at the time, the highest clock speed CPU ever produced for commercial sale.
The processor implements the CISC z/Architecture with a new superscalar, out-of-order pipeline and 100 new instructions. The instruction pipeline has 15 to 17 stages; the instruction queue can hold 40 instructions; and up to 72 instructions can be "in flight". It has four cores, each with a private 64 KB L1 instruction cache, a private 128 KB L1 data cache and a private 1.5 MB L2 cache. In addition, there is a 24 MB shared L3 cache implemented in eDRAM and controlled by two on-chip L3 cache controllers. There's also an additional shared L1 cache used for compression and cryptography operations.
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