IBM zEC12 (microprocessor)
| Produced | 2012 |
|---|---|
| Designed by | IBM |
| Max. CPU clock rate | 5.5 GHz |
| Min. feature size | 32 nm |
| Instruction set | z/Architecture (ARCHLVL 3) |
| Cores | 6 |
| L1 cache | 64+96 KB/core |
| L2 cache | 1+1 MB/core |
| L3 cache | 48 MB/chip |
| Predecessor | z196 |
| Successor | z13 |
The zEC12 microprocessor (zEnterprise EC12 or just z12) is a chip made by IBM for their zEnterprise EC12 mainframe computers, announced on August 28, 2012. Manufactured at then IBM's East Fishkill, New York fabrication plant (to be continued for ten years by now owner GlobalFoundries), the processor began shipping in the fall of 2012. IBM stated that it is the world's fastest microprocessor and is about 25% faster than its predecessor the z196.
The chip measures 597.24 mm2 and consists of 2.75 billion transistors fabricated in IBM's 32 nm CMOS silicon on insulator fabrication process, supporting speeds of 5.5 GHz, the highest clock speed CPU ever produced for commercial sale.
The processor implements the CISC z/Architecture with a superscalar, out-of-order pipeline and some new instructions mainly related to transactional execution. The cores have numerous other enhancements such as better branch prediction, out of order execution and one dedicated co-processor for compression and cryptography. The instruction pipeline has 15 to 17 stages; the instruction queue can hold 40 instructions; and up to 90 instructions can be "in flight". It has six cores, each with a private 64 KB L1 instruction cache, a private 96 KB L1 data cache, a private 1 MB L2 cache instruction cache, and a private 1 MiB L2 data cache. In addition, there is a 48 MB shared L3 cache implemented in eDRAM and controlled by two on-chip L3 cache controllers. There's also an additional shared L1 cache used for compression and cryptography operations.
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