32nm
The 32 nanometer (32 nm) node is the step following the 45 nanometer process in CMOS semiconductor device fabrication. "32 nanometer" refers to the average half-pitch (i.e., half the distance between identical features) of a memory cell at this technology level. Intel and AMD both produced commercial microchips using the 32 nanometer process in the early 2010s. IBM and the Common Platform also developed a 32 nm high-k metal gate process. Intel began selling its first 32 nm processors using the Westmere architecture on 7 January 2010.
28 nanometer was an intermediate half-node die shrink based on the 32 nanometer process.
The 32 nm process was superseded by commercial 22 nm technology in 2012.
Prototypes using 32 nm technology first emerged in the mid-2000s. In 2004, IBM demonstrated a 0.143 μm2 SRAM cell with a poly gate pitch of 135 nm, produced using electron-beam lithography and photolithography on the same layer. It was observed that the cell's sensitivity to input voltage fluctuations degraded significantly at such a small scale. In October 2006, the Interuniversity Microelectronics Centre (IMEC) demonstrated a 32 nm flash patterning capability based on double patterning and immersion lithography. The necessity of introducing double patterning and hyper-NA tools to reduce memory cell area offset some of the cost advantages of moving to this node from the 45 nm node.TSMC similarly used double patterning combined with immersion lithography to produce a 32 nm node 0.183 μm2 six-transistor SRAM cell in 2005.
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