Double patterning

Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the upcoming 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls (using spacers) would be necessary.

Although EUV has been projected to be the next-generation lithography of choice, it would still require more than one lithographic exposure, due to the foreseen need to first print a series of lines and then cut them. It is also likely more than one cut would be needed, even for EUV.

Even for electron beam lithography, single exposure appears insufficient at ~10 nm half-pitch, hence requiring double patterning.

The earliest form of multiple patterning involved simply dividing a pattern into two or three parts, each of which may be processed conventionally, with the entire pattern combined at the end in the final layer. This is sometimes called pitch splitting, since two features separated by one pitch cannot be imaged, so only skipped features can be imaged at once. It is also named more directly as "LELE" (Litho-Etch-Litho-Etch). This approach has been used for the 20 nm and 14 nm nodes. The additional cost of extra exposures was tolerated since only a few critical layers would need them. A more serious concern was the effect of feature-to-feature positioning errors (overlay). Consequently, the self-aligned sidewall imaging approach (described below) has succeeded this approach.

A "brute force" approach for patterning trenches involves a sequence of (at least) two separate exposures and etchings of independent patterns into the same layer. For each exposure, a different photoresist coating is required. When the sequence is completed, the pattern is a composite of the previously etched subpatterns. By interleaving the subpatterns, the pattern density can theoretically be increased indefinitely, the half-pitch being inversely proportional to the number of subpatterns used. For example, a 25 nm half-pitch pattern can be generated from interleaving two 50 nm half-pitch patterns, three 75 nm half-pitch patterns, or four 100 nm half-pitch patterns. The feature size reduction will most likely require the assistance of techniques such as chemical shrinks, thermal reflow, or shrink assist films. This composite pattern can then be transferred down into the final layer.

A possible application would be, for example, dividing the contact layer into two separate groups: gate contacts and source/drain contacts, each defining its own mask. IMEC recently used an approach like this to demonstrate a 45 nm node 6-transistor SRAM cell using dry lithography [3].

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