IDT WinChip Marketing sample
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Produced | From 1997 to 1999 |
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Marketed by | IDT |
Designed by | Centaur Technology |
Max. CPU clock rate | 180 Mhz to 266 Mhz |
FSB speeds | 60 MT/s to 100 MT/s |
Min. feature size | 0.35 µm to 0.25 µm |
Instruction set | x86 (IA-32) |
Microarchitecture | Single, 4-stage, pipeline in-order execution |
CPUID code | 0540h, 0541h, 0585h, 0587h, 058Ah, 0595h |
Cores | 1 |
L1 cache | 64 KiB (C6, W2, W2A and W2B) 128 KiB (W3) |
L2 cache | Motherboard dependent |
L3 cache | none |
Socket(s) | |
Successor | Cyrix III |
Package(s) | |
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The WinChip series was a low-power Socket 7-based x86 processor designed by Centaur Technology and marketed by its parent company IDT.
The design of the WinChip was quite different from other processors of the time. Instead of a large gate count and die area, IDT, using its experience from the RISC processor market, created a small and electrically efficient processor similar to the 80486, because of its single pipeline and in-order execution microarchitecture. It was of much simpler design than its Socket 7 competitors, such as AMD K5/K6 and Intel Pentium, which were superscalar and based on dynamic translation to buffered micro-operations with advanced instruction reordering (out of order execution).
WinChip was, in general, designed to perform well with popular applications that didn't do many (if any) floating point calculations. This included operating systems of the time and the majority of software used in businesses. It was also designed to be a drop-in replacement for the more complex, and thus more expensive, processors it was competing with. This allowed IDT/Centaur to take advantage of an established system platform (Intel's Socket 7).
The WinChip 2A added fractional multipliers and adopted a 100 MHz front side bus to improve memory access and L2 cache performance. It also adopted a performance rating nomenclature instead of reporting the real clock speed, similar to contemporary AMD and Cyrix processors.