Cyrix III
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| Produced | From February 2000 to Early 2001 |
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| Max. CPU clock rate | 350 MHz to 700 MHz |
| FSB speeds | 100 to 133 |
| Min. feature size | 0.18 to 0.15 |
| Instruction set | x86 |
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Cyrix III is an x86-compatible Socket 370 CPU. VIA Technologies launched the processor in February 2000. VIA had purchased both Centaur Technology and Cyrix. Cyrix III was to be based upon a core from one of the two companies.
The pre-release Cyrix III CPUs were based upon a 22 million transistor Joshua core designed by Cyrix. This CPU core was a typical Cyrix design: superscalar with speculative execution and a high IPC rate but rather low clock rates. To emphasize the higher performance of their designs compared to the competitors' offerings, Cyrix used a system with a "P-Rating" higher than the clock rate. The floating point unit of the processor had supposedly been updated from the lacklustre unit in the 6x86/MII series. When the chip reached reviewers, the weighted integer/floating-point performance was found to be fairly low compared to the competition. The fact that Cyrix 6x86-line were only 486-compatible, not 100% Pentium-compatibile, intensified the negative attention at this point.
Because the Joshua core was such a mixed result in thermal output, core size, and performance, VIA switched almost immediately to an 11 million transistor Samuel core designed by Centaur Technology. The Samuel core was a simpler design, being an evolution of the WinChip processors (the unreleased WinChip 4). Samuel was designed for higher clock speeds, with more L1 cache (but no L2), and used smaller manufacturing technology. While this version of Cyrix III still had sub-par performance compared to the competition from Intel and AMD, it was quite power efficient and consisted of only half the number of transistors of Cyrix's creation.
VIA dropped the criticized PR rating with new processors based on the Samuel core, in favor of simply distinguishing them by their actual clock speed.
The Samuel 2 core is a revision to the Samuel core. The Centaur Technology team added an on-die 64 KiB L2 cache and moved to a 150 nm manufacturing process. These changes improved per-clock performance, reduced power demands, and increased clock speed scalability.
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