Visual Instruction Set

Visual Instruction Set, or VIS, is a SIMD instruction set extension for SPARC V9 microprocessors developed by Sun Microsystems. There are five versions of VIS: VIS 1, VIS 2, VIS 2+, VIS 3 and VIS 4.

VIS 1 was introduced in 1994 and was first implemented by Sun in their UltraSPARC microprocessor (1995) and by Fujitsu in their SPARC64 GP microprocessors (2000).

VIS 2 was first implemented by the UltraSPARC III. All subsequent UltraSPARC and SPARC64 microprocessors implement the instruction set.

VIS 3 was first implemented in the SPARC T4 microprocessor.

VIS 4 was first implemented in the SPARC M7 microprocessor.

VIS is not an instruction toolkit like Intel's MMX and SSE. MMX has only 8 registers shared with the FPU stack, while SPARC processors have 32 registers, also aliased to the double-precision (64-bit) floating point registers.

As with the SIMD instruction set extensions on RISC processors, VIS strictly conform to the main principle of RISC: keep the instruction set concise and efficient.

This design is very different from comparable extensions on CISC processors, such as MMX, SSE, SSE2, SSE3, SSE4, 3DNow!.

Sometimes, programmers must use several VIS instructions to accomplish an operation that can be done with only one MMX or SSE instruction, but it should be kept in mind that fewer instructions do not automatically result in better performance.

VIS re-uses existing SPARC V9 64-bit floating point registers to hold multiple 8, 16, or 32-bit integer values. In this respect, VIS is more similar to the design of MMX than other SIMD architectures such as SSE/SSE2/AltiVec.

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