SPARC T4
| Produced | 2011 |
|---|---|
| Max. CPU clock rate | 2.85 GHz to 3.0 GHz |
| Min. feature size | 40 nm |
| Instruction set | SPARC V9 |
| Cores | 8 |
| L1 cache | 8×(16+16) kB |
| L2 cache | 8×128 kB |
| L3 cache | 4 MB |
| Predecessor | SPARC T3 |
| Successor | SPARC T5 |
| Core name(s) |
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The SPARC T4 is a SPARC multicore microprocessor introduced in 2011 by Oracle Corporation. The processor is designed to offer high multithreaded performance (8 threads per core, with 8 cores per chip), as well as high single threaded performance from the same chip. The chip is the 4th generation processor in the T-Series family. Sun Microsystems brought the first T-Series processor (UltraSPARC T1) to the market back in 2005.
The chip is the first Sun/Oracle SPARC chip to use dynamic threading and out-of-order execution. It incorporates one floating point unit and one dedicated cryptographic unit per core. The cores use the 64-bit SPARC Version 9 architecture running at frequencies between 2.85 GHz and 3.0 GHz, and are built in a 40 nm process with a die size of 403 mm2 (0.625 sq in).
An eight core, eight thread per core chip built in a 40 nm process and running at 2.5 GHz was described in Sun Microsystems' processor roadmap of 2009. It was codenamed "Yosemite Falls" and given an expected release date of late 2011. The processor was expected to introduce a new microarchitecture, codenamed "VT Core". The online technology website The Register speculated that this chip would be named "T4", being the successor to the SPARC T3. The Yosemite Falls CPU product remained on Oracle Corporation's processor roadmap after the company took over Sun in early 2010. In December 2010 the T4 processor was confirmed by Oracle's VP of hardware development to be designed for improved per-thread performance, with eight cores, and with an expected release within one year.
The processor design was presented at the 2011 Hot Chips conference. The cores (renamed "S3" from "VT") included a dual-issue 16 stage integer pipeline, and 11-cycle floating point pipeline, both giving improvements over the previous ("S2") core used in the SPARC T3 processor. Each core has associated 16 KB data and 16 KB instruction L1 caches, and a unified 128 KB L2 Cache. All eight cores share 4 MB L3 cache, and the total transistor count is approximately 855 million. The design was the first Sun/Oracle SPARC processor with out-of-order execution and was the first processor in the SPARC T-Series family to include the ability to issue more than one instruction per cycle to a core's execution units.
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