RISC instruction set

A reduced instruction set computer, or RISC (pronounced 'risk', /ɹɪsk/), is one whose instruction set architecture (ISA) has a set of attributes that allows it to have a lower cycles per instruction (CPI) than a complex instruction set computer (CISC). Various suggestions have been made regarding a precise definition of RISC, but the general concept is that of a computer that has a small set of simple and general instructions, rather than a large set of complex and specialized instructions. Another common RISC trait is their load/store architecture, where memory is only accessed through specific instructions, rather than as a part of most instructions.

Although a number of computers from the 1960s and 70s have been identified as being forerunners of RISCs, the modern concept dates to the 1980s. In particular, two projects at Stanford University and University of California, Berkeley are most associated with the popularization of this concept. Stanford's MIPS would go on to be commercialized as the successful MIPS architecture, while Berkeley's RISC gave its name to the entire concept, commercialized as the SPARC. Another success from this era were IBM's efforts that eventually led to the Power Architecture. As these projects matured, a wide variety of similar designs flourished in the late 1980s and especially the early 1990s, representing a major force in the Unix workstation market as well as embedded processors in laser printers, routers and similar products.

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