PowerPC e5500

The PowerPC e5500 is a 64-bit Power Architecture-based microprocessor core from Freescale Semiconductor. The core implements most of the core of the Power ISA v.2.06 with hypervisor support, but not AltiVec. It has a four issue, seven-stage out-of-order pipeline with a double precision FPU, three Integer units, 32/32 KB data and instruction L1 caches, 512 KB private L2 cache per core and up to 2 MB shared L3 cache. Speeds range up to 2.5 GHz, and the core is designed to be highly configurable via the CoreNet fabric and meet the specific needs of embedded applications with features like multi-core operation and interface for auxiliary application processing units (APU).

The e5500 is based on the e500mc core and adds some new instructions introduced in the Power Architecture 2.06 specification, namely some byte- and bit-level acceleration; Parity, Population count, Bit permute and Compare byte. The FPU is taken straight from the PowerPC e600 core, which is a classic fully pipelined dual precision IEEE 754 unit running at full core speed and supports conversion between 64-bit floats and integers, effectively twice as fast as the FPU in e500mc. The e5500 also introduces an enhanced branch prediction unit with an 8-entry link stack.

The e5500 core is the first 64-bit Power Architecture core designed solely by Freescale and was introduced at Freescale Technology Forum in June 2010. Simulated models were available in July 2010, hard samples in late 2010 and full scale manufacturing the second half of 2011. Freescale have used the e700 and NG-64 monikers to refer to a very similarly speced core since 2004, but they are not the same product.

...
Wikipedia