PowerPC e500

The PowerPC e500 is a 32-bit Power Architecture-based microprocessor core from Freescale Semiconductor. The core is compatible with the older PowerPC Book E specification as well as the Power ISA v.2.03. It has a dual issue, seven-stage pipeline with FPUs (from version 2 onwards), 32/32 KiB data and instruction L1 caches and 256, 512 or 1024 KiB L2 frontside cache. Speeds range from 533 MHz up to 1.5 GHz, and the core is designed to be highly configurable and meet the specific needs of embedded applications with features like multi-core operation interface for auxiliary application processing units (APU).

e500 powers the high-performance PowerQUICC III system on a chip (SoC) network processors and they all share a common naming scheme, MPC85xx. Freescale's new QorIQ is the evolutionary step from PowerQUICC III and will also be based on e500 cores.

There are three versions of the e500 core, namely the original e500v1, the e500v2 and the e500mc.

A 64-bit evolution of the e500mc core is called the e5500 core and was introduced in 2010.

Key improvements in the e500v2 over the e500v1 include:

Freescale introduced the e500mc in the QorIQ family of chips in June 2008. The e500mc has the following features:

All PowerQUICC 85xx devices are based on e500v1 or e500v2 cores, most of them on the e500v2.

In June 2008 Freescale announced the QorIQ brand, microprocessors based on the e500 family of cores.

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