Motorola 88000
| Designer | Motorola |
|---|---|
| Bits | 32-bit |
| Introduced | 1988 |
| Design | RISC |
| Type | Register-Register |
| Encoding | Fixed |
| Branching | Compare and branch |
| Endianness | Bi |
| Extensions | Graphics instructions (88110 only) |
| Open | No |
| Registers | |
| General purpose | 32 32-bit |
| Floating point | 32 80-bit (88110 only) |
The 88000 (m88k for short) is a RISC instruction set architecture (ISA) developed by Motorola. The 88000 was Motorola's attempt at a home-grown RISC architecture, started in the 1980s. The 88000 arrived on the market some two years after the competing SPARC and MIPS. Due to the late start and extensive delays releasing the second-generation MC88110, the m88k achieved very limited success outside of the MVME platform and embedded controller environments.
Originally called the 78000 as a homage to their famed 68000 series, the design went through a tortuous development path, including the number change, before finally emerging in April 1988. This initial version generally required a separate MMU, and saw little use. A follow-on version combining the CPU and MMU was planned. In the late 1980s several companies were actively watching the 88000 series for future use, including NeXT, Apple Computer and Apollo Computer, but all gave up by the time the 88110 was available in 1990.
There was an attempt to popularize the system with the 88open group, similar to what Sun Microsystems was attempting with their SPARC design. It appears to have failed in any practical sense.
In the early 1990s Motorola joined the AIM effort to create a new RISC architecture based on the IBM POWER architecture. They worked a few features of the 88000 into the new PowerPC architecture to offer their customer base some sort of upgrade path. At that point the 88000 was dumped as soon as possible.
Like the 68000 before it, the 88000 was considered to be a very "clean" design. It was a pure 32-bit load/store architecture, using separate instruction and data caches (Harvard architecture), and separate data and address buses. It had a small but powerful command set, and, like all Motorola CPUs, did not use memory segmentation.
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