Knights Landing (microarchitecture)
| Max. CPU clock rate | 1.053 GHz to 1.7 GHz |
|---|---|
| Cores |
|
| L1 cache | 64 KB per core |
| L2 cache | 512 KB per core |
| Created | 2012 |
| Transistors |
22 nm transistors (Tri-Gate) 14 nm transistors (Tri-Gate) |
| Architecture | x64 |
| Extensions | |
| Socket(s) |
|
| Brand name(s) |
Xeon Phi is a brand name given to a series of manycore processors designed, manufactured, marketed, and sold by Intel, targeted at supercomputing, enterprise, and high-end workstation markets.
Initially in the form of PCIe-based add-on cards, a second generation product, codenamed Knights Landing was announced in June 2013. These second generation chips could be used as a standalone CPU, not just as an add-in card.
In June 2013, the Tianhe-2 supercomputer at the National Supercomputing Center in Guangzhou (NSCC-GZ) was announced as the world's fastest supercomputer (As of November 2016, it is #2). It uses Intel Xeon Phi coprocessors and Ivy Bridge-EP Xeon processors to achieve 33.86 petaFLOPS.
Competitors include Nvidia's Tesla-branded product lines.
The Larrabee microarchitecture (in development since 2006) introduced very wide (512-bit) SIMD units to a x86 architecture based processor design, extended to a cache-coherent multiprocessor system connected via a ring bus to memory; each core was capable of four-way multithreading. Due to the design being intended for GPU as well as general purpose computing the Larrabee chips also included specialised hardware for texture sampling. The project to produce a retail GPU product directly from the Larrabee research project was terminated in May 2010.
Another contemporary Intel research project implementing x86 architecture on a many-multicore processor was the 'Single-chip Cloud Computer' (prototype introduced 2009), a design mimicking a cloud computing computer datacentre on a single chip with multiple independent cores: the prototype design included 48 cores per chip with hardware support for selective frequency and voltage control of cores to maximize energy efficiency, and incorporated a mesh network for interchip messaging. The design lacked cache-coherent cores and focused on principles that would allow the design to scale to many more cores.
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