Verilog-A

Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS.

Verilog-A was created out of a need to standardize the Spectre behavioral language in face of competition from VHDL (an IEEE standard), which was absorbing analog capability from other languages (e.g. MAST). Open Verilog International (OVI, the body that originally standardized Verilog) agreed to support the standardization, provided that it was part of a plan to create Verilog-AMS — a single language covering both analog and digital design. Verilog-A was an all-analog subset of Verilog-AMS that was the first phase of the project.

There was considerable delay (possibly procrastination) between the first Verilog-A language reference manual and the full Verilog-AMS, and in that time Verilog moved to the IEEE, leaving Verilog-AMS behind at Accellera.

The email log from 2000AD can be found here.

Verilog-A standard does not exist stand-alone - it is part of the complete Verilog-AMS standard. Its LRM is available at the Accellera website. However, the initial and subsequent releases can be found here, with what will probably be the final release here since future work will leverage the new net-type capabilities in SystemVerilog. Built-in types like "wreal" in Verilog-AMS will become user-defined types in SystemVerilog more in line with the VHDL methodology.

This first example gives a first demonstration of modeling in Verilog-A:

This Verilog-AMS example implements an ideal diode, by defining the current through the branch (a,c) depending on voltage at branch terminals (a), (c), and the ambient temperature of the simulated circuit:

For a simple DC voltage source, the branch voltage is set to the constant (DC) value:

A sine voltage generator can use the built-in sin() function:

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