SystemVerilog
SystemVerilog logo
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| Paradigm |
Structured (design) Object-oriented (verification) |
|---|---|
| First appeared | 2002 |
| Stable release |
IEEE 1800-2012 / February 21, 2013
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| Typing discipline | Static, weak |
| Filename extensions | .sv |
| Influenced by | |
| Verilog, Vera, VHDL | |
In the semiconductor and electronic design industry, SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog.
SystemVerilog started with the donation of the Superlog language to Accellera in 2002. The bulk of the verification functionality is based on the OpenVera language donated by Synopsys. In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005. In 2009, the standard was merged with the base Verilog (IEEE 1364-2005) standard, creating IEEE Standard 1800-2009. The current version is IEEE standard 1800-2012.
The feature-set of SystemVerilog can be divided into two distinct roles:
The remainder of this article discusses the features of SystemVerilog not present in Verilog-2005.
There are two types of data lifetime specified in SystemVerilog: static and automatic. Automatic variables are created the moment program execution comes to the scope of the variable. Static variables are created at the start of the program's execution and keep the same value during the entire program's lifespan, unless assigned a new value during execution.
Any variable that is declared inside a task or function without specifying type will be considered automatic. To specify that a variable is automatic place the "automatic" keyword in the declaration before the type, e.g., "automatic int x;". The "static" keyword is used in the same way.
Enhanced variable types add new capability to Verilog's "reg" type:
Verilog-1995 and -2001 limit reg variables to behavioral statements such as RTL code. SystemVerilog extends the reg type so it can be driven by a single driver such as gate or module. SystemVerilog names this type "logic" to remind users that it has this extra capability and is not a hardware register. The names "logic" and "reg" are interchangeable. A signal with more than one driver needs to be declared a net type such as "wire" so SystemVerilog can resolve the final value.
Multidimensional packed arrays unify and extend Verilog's notion of "registers" and "memories":
Classical Verilog permitted only one dimension to be declared to the left of the variable name. SystemVerilog permits any number of such "packed" dimensions. A variable of packed array type maps 1:1 onto an integer arithmetic quantity. In the example above, each element of my_pack may be used in expressions as a five-bit integer. The dimensions to the right of the name (32 in this case) are referred to as "unpacked" dimensions. As in Verilog-2001, any number of unpacked dimensions is permitted.
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