Unbuffered memory

Registered (also called buffered) memory modules have a register between the DRAM modules and the system's memory controller. They place less electrical load on the memory controller and allow single systems to remain stable with more memory modules than they would have otherwise. When compared with registered memory, conventional memory is usually referred to as unbuffered memory or unregistered memory. When manufactured as a dual in-line memory module (DIMM), a registered memory module is called an RDIMM, while unregistered memory is called UDIMM.

Registered memory is often more expensive because of the lower number of units sold and additional circuitry required, so it is usually found only in applications where the need for scalability and robustness outweighs the need for a low price – for example, registered memory is usually used in servers.

Although most registered memory modules also feature error-correcting code memory (ECC), it is also possible for registered memory modules to not be error-correcting or vice versa. Unregistered ECC memory is, for example, supported and used in workstation or entry-level server motherboards that do not support very large amounts of memory.

Normally, there is a performance penalty for using registered memory. Each read or write is buffered for one cycle between the memory bus and the DRAM, so the registered RAM can be thought of as running one clock cycle behind the equivalent unregistered DRAM. With SDRAM, this only applies to the first cycle of a burst.

However, this performance penalty is not universal. There are other factors involved in memory access speed. For example, the Intel Westmere 5600 series of processors access memory using interleaving, wherein memory access is distributed across three channels. If two memory DIMMs are used per channel, this “results in a reduction of maximum memory bandwidth for 2DPC (DIMMs per channel) configurations with UDIMM by some 5% in comparison to RDIMM.” (p. 14). This is because "when you go to two DIMMs per memory channel, due to the high electrical loading on the address and control lines, the memory controller uses a '2T' or '2N' timing for UDIMMs. Consequently, every command that normally takes a single clock cycle is stretched to two clock cycles to allow for settling time. Therefore, for two or more DIMMs per channel, RDIMMs will have lower latency and better bandwidth than UDIMMs."

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