SuperH
| Designer | Hitachi Ltd. |
|---|---|
| Bits | 32-bit (32 → 64) |
| Introduced | 1990s |
| Design | RISC |
| Encoding | Fixed |
| Endianness | Bi |
SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.
As of 2015[update], many of the original patents for the SuperH architecture are expiring and the SH2 CPU has been reimplemented as open source hardware under the name J2.
The SuperH processor core family was first developed by Hitachi in the early 1990s. Hitachi has developed a complete group of upward compatible instruction set CPU cores. The SH-1 and the SH-2 were used in the Sega Saturn and Sega 32X. These cores have 16-bit instructions for better code density than 32-bit instructions, which was a great benefit at the time, due to the high cost of main memory.
A few years later the SH-3 core was added to the SH CPU family; new features included another interrupt concept, a memory management unit (MMU) and a modified cache concept. The SH-3 core also got a DSP extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine, this core was unifying the DSP and the RISC processor world. A derivative was also used with the original SH-2 core.
...
Wikipedia