SSE5

The SSE5 (short for Streaming SIMD Extensions version 5) was a SIMD instruction set extension proposed by AMD on 30 August 2007 as a supplement to the 128-bit SSE core instructions in the AMD64 architecture.

AMD chose not to implement SSE5 as originally proposed. In May 2009, AMD replaced SSE5 with three smaller instruction set extensions named as XOP, FMA4, and CVT16, which retain the proposed functionality of SSE5, but encode the instructions differently for better compatibility with Intel's proposed AVX instruction set.

The three SSE5-derived instruction sets were introduced in the Bulldozer processor core, released in October 2011 on a 32 nm process.

AMD's SSE5 extension bundle does not include the full set of Intel's SSE4 instructions, making it a competitor to SSE4 rather than a successor.

This complicates software development. It is recommended practice for a program to test for the presence of instruction set extensions by means of the CPUID instruction before entering a code path which depends upon those instructions to function correctly. For maximum portability, an optimized application will require three code paths: a base code path for compatibility with older processors (from either vendor), a separately optimized Intel code path exploiting SSE4 or AVX, and a separately optimized AMD code path exploiting SSE5.

Due to this proliferation, benchmarks between Intel and AMD processors increasingly reflect the cleverness or implementation quality of the divergent code paths rather than the strength of the underlying platform.

The proposed SSE5 instruction set consisted of 170 instructions (including 46 base instructions), many of which are designed to improve single-threaded performance. Some SSE5 instructions are 3-operand instructions, the use of which will increase the average number of instructions per cycle achievable by x86 code. Selected new instructions include:

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