NetBurst (microarchitecture)
| L1 cache | 8 KB to 16 KB per core |
|---|---|
| L2 cache | 128 KB to 2048 KB 256 KB to 2048 KB (Xeon) |
| L3 cache | 4 MB to 16 MB shared |
| Model | Celeron Series |
| Created | November 20, 2000 |
| Transistors | 42M 180 nm (B2, C1, D0, E0) |
| Architecture | NetBurst x86 |
| Instructions | MMX |
| Extensions | |
| Socket(s) | |
| Predecessor | P6 |
| Successor | Intel Core |
The NetBurst microarchitecture, called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of CPUs made by Intel. The first CPU to use this architecture was the Willamette-core Pentium 4, released on November 20, 2000 and the first of the Pentium 4 CPUs; all subsequent Pentium 4 and Pentium D variants have also been based on NetBurst. In mid-2001, Intel released the Foster core, which was also based on NetBurst, thus switching the Xeon CPUs to the new architecture as well. Pentium 4-based Celeron CPUs also use the NetBurst architecture.
NetBurst was replaced with the Core microarchitecture, released in July 2006.
The NetBurst microarchitecture includes features such as Hyper-Threading, Hyper Pipelined Technology, Rapid Execution Engine and Replay System which are firsts in this particular microarchitecture.
Hyper-threading is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multiple tasks at once) performed on x86 microprocessors. Intel introduced it with NetBurst processors in 2002. Later Intel reintroduced it with Nehalem microarchitecture after its absence in Core microarchitecture.
"Northwood" and "Willamette" feature an external Front-Side Bus that runs at 100 MHz and is 64-bits wide, but is also quad-pumped, thus giving 3.2 GB/s of memory bandwidth. The Intel "Northwood" i850 chipset with dual-channel RD-RAM can provide 3.2 GB/s of memory bandwidth. The "Presler" has an 800 MHz front-side bus, 64-bits wide, capable of transferring 6.4 GB/s, with 800 MHz DDR2 memory.
This is the name given to the 20-stage instruction pipeline within the Willamette core. This is a significant increase in the number of stages when compared to the Pentium III, which had only 10 stages in its pipeline. The Prescott core has a 31-stage pipeline (some stages are just moving data around the CPU). Although a deeper pipeline has an increased branch misprediction penalty, the greater number of stages in the pipeline allow the CPU to have higher clock speeds which was thought to offset any loss in performance. A smaller instructions per clock (IPC) is an indirect consequence of pipeline depth—a matter of design compromise (a small number of long pipelines has a smaller IPC than a greater number of short pipelines). Another drawback of having more stages in a pipeline is an increase in the number of stages that need to be traced back in the event that the branch predictor makes a mistake, increasing the penalty paid for a mis-prediction. To address this issue, Intel devised the Rapid Execution Engine and has invested a great deal into its branch prediction technology, which Intel claims reduces branch mispredictions by 33% over Pentium III.
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