Massbus

The Massbus is a high-performance computer input/output bus designed in the 1970s by the Digital Equipment Corporation of Maynard, Massachusetts.

The bus was used by Digital to interconnect its highest-performance computers with magnetic disk and magnetic tape storage equipment. The use of a common bus allowed the PDP-10, PDP-11, and VAX computer families to share a common set of peripherals. An additional business objective was to provide a subsystem entry price well below that of IBM storage subsystems which used large and expensive controllers unique to each storage technology and optimized for connecting large numbers of storage devices.

The bus is logically implemented as two separate sections:

Massbus storage devices each contain their own autonomous controller units, allowing fully overlapped operation of multiple storage units connected to a single Massbus. The interface between the computer and the Massbus is basically a pass-through device that allows connection of the common Massbus to the individual computer's internal buses (whether PDP-10 memory bus, Unibus, PDP-11/70 cache bus, or VAX Synchronous Backplane Interconnect). Whenever a storage controller has a data transfer ready, it arbitrates for the use of the Massbus's synchronous data channel.

The bus is physically implemented in two forms:

The less-expensive flat grey cables are used within shielded equipment enclosures while the round cables are used to connect the enclosures. Transition headers allowed switching freely between the two types of cables and a single Massbus can be daisy-chained between the controller and up to eight mass storage devices. A very heavy ground conductor (wire) also usually joins the equipment.

Disk: (capacities noted are raw, not formatted)

Note the RM02 uses a different drive pulley to slow the disk transfers to a level compatible with a Unibus-based PDP11. The RM03 spun at full speed, and is supported on the pdp11/70 and larger systems. Curiously enough the DECSYSTEM 2020 can support an RM03 with its Unibus-based interface due to a highly buffered Unibus-to-memory interface.

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