I686
| L1 cache | 32 KB |
|---|---|
| L2 cache | 128 KB to 512 KB 256 KB to 2048 KB (Xeon) |
| Model | Celeron Series |
| Created | November 1, 1995 |
| Transistors | 7.5M 350 nm |
| Architecture | P6 x86 |
| Instructions | MMX |
| Extensions | |
| Socket(s) | |
| Predecessor | P5 |
| Successor | NetBurst |
| Variant | Pentium M |
 |
|
| L1 cache | 64KB |
|---|---|
| L2 cache | 512 KB to 2048 KB |
| Model | A100 Series |
| Created | 2003 |
| Transistors | 77M 130 nm (B1, B2) |
| Architecture | P6 x86 |
| Instructions | MMX |
| Extensions | |
| Socket | Socket M |
| Predecessor | NetBurst |
| Successor | Enhanced Pentium M |
 |
|
| L1 cache | 64 KB |
|---|---|
| L2 cache | 1 MB to 2 MB 2 MB (Xeon) |
| Model | Celeron M Series |
| Created | 2006 |
| Transistors | 151M 65 nm (C0, D0) |
| Architecture | P6 x86 |
| Instructions | MMX |
| Extensions | |
| Socket | Socket M |
| Predecessor | Pentium M |
| Successor | Intel Core |
The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is sometimes referred to as i686. It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from the P6 microarchitecture.
The P6 core was the sixth generation Intel microprocessor in the x86 line. The first implementation of the P6 core was the Pentium Pro CPU in 1995, the immediate successor to the original Pentium design (P5).
Some techniques first used in the x86 space in the P6 core include:
The P6 architecture lasted three generations from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC). The P6 line of processing cores was succeeded with the NetBurst (P68) architecture which appeared with the introduction of Pentium 4. This was a completely different design based on the use of very long pipelines that favoured high clock speed at the cost of lower IPC, and higher power consumption.
Upon release of the Pentium 4-M and Mobile Pentium 4, it was quickly realized that the new mobile NetBurst processors were not ideal for mobile computing. The Netburst-based processors were simply not as efficient per clock or per watt compared to their P6 predecessors. Mobile Pentium 4 processors ran much hotter than Pentium III-M processors and didn't offer significant performance advantages. Its inefficiency affected not only the cooling system complexity, but also the all-important battery life.
Realizing their new microarchitecture wasn't the best choice for the mobile space, Intel went back to the drawing board for a design that would be optimally suited for this market segment. The result was a modernized P6 design called the Pentium M:
Design Overview
The Pentium M was the most power efficient x86 processor for notebooks for several years, consuming a maximum of 27 watts at maximum load and 4-5 watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival the Mobile Pentium 4 clocked over 1 GHz higher (the fastest-clocked Mobile Pentium 4 compared to the fastest-clocked Pentium M) and equipped with much more memory and bus bandwidth. The first Pentium M family processors ("Banias") internally support PAE but do not show the PAE support flag in their CPUID information; this causes some operating systems (primarily Linux distributions) to refuse to boot on such processors since PAE support is required in their kernels.
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