HMOs

In integrated circuits, depletion-load NMOS is a form of digital logic family that uses only a single power supply voltage, unlike earlier nMOS logic families that needed more than one different power supply voltage. Although manufacturing these integrated circuits required additional processing steps, improved switching speed and the elimination of the extra power supply made this logic family the preferred choice for many microprocessors and other logic elements.

Some depletion-load nMOS designs are still produced, typically in parallel with newer CMOS counterparts; one example of this is the Z84015 and Z84C15.

Depletion-mode n-type MOSFETs as load transistors allow single voltage operation and achieve greater speed than possible with pure enhancement-load devices. This is partly because the depletion-mode MOSFETs can be a better current source approximation than the simpler enhancement-mode transistor can, especially when no extra voltage is available (one of the reasons early pMOS and nMOS chips demanded several voltages).

The inclusion of depletion-mode n-MOS transistors in the manufacturing process demanded additional manufacturing steps compared to the simpler enhancement-load circuits; this is because depletion-load devices are formed by increasing the amount of dopant in the load transistors channel region, in order to adjust their threshold voltage. This is normally performed using ion implantation.

In the late 1960s, bipolar junction transistors were a hundred times as fast as the (p-channel) MOS transistors then used and were much more reliable, but they also consumed much more power, required more area, and demanded a more complicated manufacturing process. MOS ICs were considered interesting but inadequate for supplanting the fast bipolar circuits in anything but niche markets, such as low power applications. One of the reasons for the low speed was that MOS transistors had gates made of aluminum which led to considerable parasitic capacitances using the manufacturing processes of the time. The introduction of transistors with gates of polycrystalline silicon (that became the de facto standard from the mid-1970s to early 2000s) was an important first step in order to reduce this handicap. This new self-aligned silicon-gate transistor was introduced by Federico Faggin at Fairchild Semiconductor in early 1968; it was a refinement (and the first working implementation) of ideas and work by John C. Sarace, Tom Klein and Robert W. Bower (around 1966–67) for a transistor with less parasitic capacitances that could be manufactured as part of an IC (and not only as a discrete component). This new type of pMOS transistor was 3–5 times as fast (per watt) as the aluminum-gate pMOS transistor, and it needed less area, had much lower leakage and higher reliability. The same year, Faggin also built the first IC using the new transistor type, the Fairchild 3708 (8-bit analog multiplexer with decoder), which demonstrated a substantially improved performance over its metal-gate counterpart. In less than 10 years, the silicon gate MOS transistor replaced bipolar circuits as the main vehicle for complex digital ICs.

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