Self-aligned gate

In electronics, a self-aligned gate is a transistor manufacturing feature whereby a refractory gate electrode region of a MOSFET transistor is used as a mask for the doping of the source and drain regions. This technique ensures that the gate will slightly overlap the edges of the source and drain.

The use of self-aligned gates is one of the many innovations that led to the large increase in computing power in the 1970s. Self-aligned gates are still used in most modern integrated circuit processes.

The self-aligned gate is used to eliminate the need to align the gate electrode to the source and drain regions of a MOS transistor during the fabrication process. With self-aligned gates the parasitic overlap capacitances between gate and source, and gate and drain are substantially reduced, leading to MOS transistors that are faster, smaller and more reliable than transistors made without them. After the early experimentation with different gate materials (aluminum, molybdenum, amorphous silicon) the industry almost universally adopted self-aligned gates made with polycrystalline silicon, the so-called Silicon Gate Technology (SGT), which had many additional benefits over the reduction of parasitic capacitances. One important feature of SGT was that the silicon gate was entirely buried under top quality thermal oxide (one of the best insulators known), making it possible to create new device types, not feasible with conventional technology or with self-aligned gates made with other materials. Particularly important are charge coupled devices (CCD), used for image sensors, and non-volatile memory devices using floating silicon-gate structures. These devices dramatically enlarged the range of functionality that could be achieved with solid state electronics.

Innovations that made Self-Aligned Gate Technology possible

Certain innovations were required in order to make self-aligned gates:

Prior to these innovations, self-aligned gates had been demonstrated on metal-gate devices, but their real impact was on silicon-gate devices.

The aluminum-gate MOS process technology, developed in the mid-sixties, started with the definition and doping of the source and drain regions of MOS transistors, followed by the gate mask that defined the thin-oxide region of the transistors. With additional processing steps, an aluminum gate would then be formed over the thin-oxide region completing the device fabrication. Due to the inevitable misalignment of the gate mask with respect to the source and drain mask, it was necessary to have a fairly large overlap area between the gate region and the source and drain regions, to ensure that the thin-oxide region would bridge the source and drain, even under worst-case misalignment. This requirement resulted in gate-to-source and gate-to-drain parasitic capacitances that were large and variable from wafer to wafer, depending on the misalignment of the gate oxide mask with respect with the source and drain mask. The result was an undesirable spread in the speed of the integrated circuits produced, and a much lower speed than theoretically possible if the parasitic capacitances could be reduced to a minimum. The overlap capacitance with the most adverse consequences on performance was the gate-to-drain parasitic capacitance, Cgd, which, by the well-known Miller effect, augmented the gate-to-source capacitance of the transistor by Cgd multiplied by the gain of the circuit to which that transistor was a part. The impact was a considerable reduction in the switching speed of transistors.

...
Wikipedia