HAL SPARC64
| Produced | 1995 |
|---|---|
| Designed by | HAL Computer Systems |
| Common manufacturer(s) | |
| Max. CPU clock rate | 101 MHz to 118 MHz |
| Instruction set | SPARC V9 |
| Cores | 1 |
| Produced | From 1996 to 1998 |
|---|---|
| Designed by | HAL Computer Systems |
| Common manufacturer(s) | |
| Max. CPU clock rate | 141–161 MHz |
| Instruction set | SPARC V9 |
| Produced | From 1997 to 2002 |
|---|---|
| Designed by | HAL Computer Systems |
| Common manufacturer(s) | |
| Max. CPU clock rate | 225–275 MHz to 600–810 MHz |
| Instruction set | SPARC V9 |
SPARC64 is a microprocessor developed by HAL Computer Systems and fabricated by Fujitsu. It implements the SPARC V9 instruction set architecture (ISA), the first microprocessor to do so. SPARC64 was HAL's first microprocessor and was the first in the SPARC64 brand. It operates at 101 and 118 MHz. The SPARC64 was used exclusively by Fujitsu in their systems; the first systems, the Fujitsu HALstation Model 330 and Model 350 workstations, were formally announced in September 1995 and were introduced in October 1995, two years late. It was succeeded by the SPARC64 II (previously known as the SPARC64+) in 1996.
The SPARC64 is a superscalar microprocessor that issues four instructions per cycle and executes them out of order. It is a multichip design, consisting of seven dies: a CPU die, MMU die, four CACHE dies and a CLOCK die.
The CPU die contains the majority of logic, all of the execution units and a level 0 (L0) instruction cache. The execution units consist of two integer units, address units, floating-point units (FPUs), memory units. The FPU hardware consists of a fused multiply add (FMA) unit and a divide unit. But the FMA instructions are really fused (that is, with a single rounding) only as of SPARC64 VI. The FMA unit is pipelined and has a four-cycle latency and a one-cycle-throughput. The divide unit is not pipelined and has significantly longer latencies. The L0 instruction cache has a capacity of 4 KB, is direct-mapped and has a one-cycle latency.
The CPU die is connected to the CACHE and MMU dies by ten 64-bit buses. Four address buses carrying virtual addresses lead out to each cache die. Two data buses write data from the register file to the two CACHE dies that implement the data cache. Four buses, one from each CACHE die, deliver data or instructions to the CPU.
The CPU die contained 2.7 million transistors, has dimensions of 17.53 mm by 16.92 mm for an area of 297 mm2 and has 817 signal bumps and 1,695 power bumps.
The MMU die contains the memory management unit, cache controller and the external interfaces. The SPARC64 has separate interfaces for memory and input/output (I/O). The bus used to access the memory is 128 bits wide. The system interface is the HAL I/O (HIO) bus, a 64-bit asynchronous bus. The MMU has a die area of 163 mm2.
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