Floor planning

In electronic design automation, a floorplan of an integrated circuit is a schematic representation of tentative placement of its major functional blocks.

In modern electronic design process floorplans are created during the floorplanning design stage, an early stage in the hierarchical approach to integrated circuit design.

Depending on the design methodology being followed, the actual definition of a floorplan may differ.

Floorplanning takes in some of the geometrical constraints in a design. Examples of this are:

In some approaches the floorplan may be a partition of the whole chip area into axis aligned rectangles to be occupied by IC blocks. This partition is subject to various constraints and requirements of optimization: block area, aspect ratios, estimated total measure of interconnects, etc.

Finding good floorplans has been a research area in combinatorial optimization. Most of the problems related to finding optimal floorplans are NP-hard, i.e., require vast computational resources. Therefore, the most common approach is to use various optimization heuristics for finding good solutions.

Another approach is to restrict design methodology to certain classes of floorplans, such as sliceable floorplans.

A sliceable floorplan is a floorplan that may be defined recursively as described below.

Sliceable floorplans have been used in a number of early Electronic Design Automation tools for a number of reasons. Sliceable floorplans may be conveniently represented by binary trees (more specifically, k-d trees), which correspond to the order of slicing. More importantly, a number of NP-hard problems with floorplans have polynomial time algorithms when restricted to sliceable floorplans.

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