Diamondville (microprocessor)

Bonnell

Intel Atom logo
Produced	2008–present
Common manufacturer(s)	Intel
Max. CPU clock rate	600 MHz to 2.13 GHz
FSB speeds	400 MHz to 667 MHz
Instruction set	Intel Atom x86
Cores	1, 2
Instructions	MMX
Extensions	IA-32, x86-64, SSE, SSE2, SSE3, SSSE3
Successor	Silvermont
Package(s)	441-ball µFCBGA
Core name(s)	Silverthorne Diamondville Pineview Tunnel Creek Lincroft Stellarton Sodaville Cedarview

Bonnell is a CPU microarchitecture used by Intel Atom processors which can execute up to two instructions per cycle. Like many other x86 microprocessors, it translates x86 instructions (CISC instructions) into simpler internal operations (sometimes referred to as micro-ops, effectively RISC style instructions) prior to execution. The majority of instructions produce one micro-op when translated, with around 4% of instructions used in typical programs producing multiple micro-ops. The number of instructions that produce more than one micro-op is significantly fewer than the P6 and NetBurst microarchitectures. In the Bonnell microarchitecture, internal micro-ops can contain both a memory load and a memory store in connection with an ALU operation, thus being more similar to the x86 level and more powerful than the micro-ops used in previous designs. This enables relatively good performance with only two integer ALUs, and without any instruction reordering, speculative execution or register renaming. The Bonnell microarchitecture therefore represents a partial revival of the principles used in earlier Intel designs such as P5 and the i486, with the sole purpose of enhancing the performance per watt ratio. However, Hyper-Threading is implemented in an easy (i.e. low-power) way to employ the whole pipeline efficiently by avoiding the typical single thread dependencies.