14 nm

The 14 nanometer (14 nm) semiconductor device fabrication node is the technology node following the 22 nm/(20 nm) node. The naming of this technology node as "14 nm" came from the International Technology Roadmap for Semiconductors (ITRS). One nanometer (nm) is one billionth of a meter. The smallest commercial chips use 10nm technology. An average chip is about the size of a quarter.

The first 14 nm scale devices were shipped to consumers by Intel in 2014.

14 nm resolution is difficult to achieve in a polymeric resist, even with electron beam lithography. In addition, the chemical effects of ionizing radiation also limit reliable resolution to about 30 nm, which is also achievable using current state-of-the-art immersion lithography. Hardmask materials and multiple patterning are required.

A more significant limitation comes from plasma damage to low-k materials. The extent of damage is typically 20 nm thick, but can also go up to about 100 nm. The damage sensitivity is expected to get worse as the low-k materials become more porous.

For comparison, the atomic radius of an unconstrained silicon is 0.11 nm. Thus about 90 Si atoms would span the channel length, leading to substantial leakage.

Tela Innovations and Sequoia Design Systems developed a methodology allowing double exposure for the 14 nm node. c.2010.

Samsung and Synopsys have also begun implementing double patterning in 22 nm and 16 nm design flows.

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