Zorro III

Released as the expansion bus of the Commodore Amiga 3000 in 1990, the Zorro III computer bus was used to attach peripheral devices to an Amiga motherboard. Designed by Commodore International lead engineer Dave Haynie, the 32-bit Zorro III replaced the 16-bit Zorro II bus used in the Amiga 2000. As with the Zorro II bus, Zorro III allowed for true Plug and Play autodetection (similar to, and prior to, the PC's PCI bus) wherein devices were dynamically allocated the resources they needed on boot.

Zorro III continued Zorro II's direct memory-mapped address design (unlike 80x86 processors, the MC68K family used in the Amiga did not have a separate I/O address mechanism). Just as with Zorro II on 24-bit systems, Zorro III reserved a large chunk of 32-bit real memory address space for large memory mapped cards, a smaller chunk with smaller allocation granularity for "I/O" type board. Zorro III was never supported on 24-bit address or 16-bit data devices—it required a full 32-bit CPU. The CPU could directly address any Zorro III device as memory, so Zorro memory expansions could be made (and were made) as well as it being possible to use video memory on a video card to be as system RAM.

As an asynchronous bus, Zorro III specified bus cycles of set lengths during which a transaction conforming to the specifications of the bus could be carried out. The initial implementation of Zorro III was in Commodore's "Fat" Buster (BUS conTrollER) gate array, assisted by a very high speed PAL and numerous TTL buffer chips for bus buffering, isolation, and multiplexing. The Amiga 4000 implementation was fundamentally the same, but integrated a second gate-array to replace the TTL buffers. The Buster chip provided bus arbitration, translation between the MC68030 bus protocols and either Zorro II or Zorro III bus cycles (geographically mapped based on the Zorro bus address), and a vectored interrupt mechanism, generally not used. Zorro II bus masters were legal bus hogs, but Zorro III devices were fairly arbitrated and had controller-limited bus tenure.

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