Teraflops Research Chip

The Teraflops Research Chip (also called Polaris) is a research manycore processor, containing 80 cores developed by Intel Corporation's Tera-Scale Computing Research Program. The processor was officially announced February 11, 2007 and shown working at the 2007 International Solid-State Circuits Conference. Features of the processor include dual floating point engines, sleeping-core technology, self-correction, fixed-function cores, and three-dimensional memory stacking. The purpose of the chip is to explore the possibilities of Tera-Scale architecture (the process of creating processors with more than four cores) and to experiment with various forms of networking and communication within the next generation of processors.

The processor consists of 80 individual cores on a single chip. The cores are different from the cores used in today's mainstream multi-processors in that they are much simpler in design. The same parts and ideas that went into constructing today's generation of processors were used in the new processor. These parts and ideas are simply reconstructed in a fashion which defines the new tera-scale era of processor architecture and allow for more than four cores to function on one chip.

Each of the cores on board the teraflops research chip contains two floating point engines.

The new tera-scale technology which allows for so many cores to be integrated on one chip also allows for better load distribution and a decreased chance of overheating. If a core is overloaded then the heat produced by that core increases, which reflects a decrease in efficiency and a waste of energy. In the teraflops research chip, if some of the cores are being overloaded, that load can just be delegated to other cores, resulting in a load distribution which does not create as much heat. The processor introduces a notion of sleeping cores. To further power efficiency and optimize the ratio between computing usage and power consumption, cores that are not in use or are not needed will sleep. In other words, they will not be powered or operational other than to perform their communication duties.

Along with 80 cores, the chip also contains 80 routers. Each core has a dedicated router which is responsible for the communication of that core with all other cores and components of the processor. The router uses a five port system with 1 port going to each of the surrounding cores and one going to the DRAM (the processors local memory). The chip is laid out in an 8 core by 10 core format. Each of the 8 cores in any of the 10 rows, called nodes, has the ability to communicate directly with other cores within the same node. Communication between nodes and to other processor components is directed through a routing system. The on-die interconnect fabric which the cores use to communicate with each other is currently being researched. One option being considered is the ring topology, which consists of various sized ring networks being integrated within each other to connect the cores. A more flexible and likely solution is the mesh topology in which the cores will be connected on a grid layout.

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