Successive approximation ADC
A successive approximation ADC is a type of analog-to-digital converter that converts a continuous analog waveform into a discrete digital representation via a binary search through all possible quantization levels before finally converging upon a digital output for each conversion.
Key
The successive approximation analog-to-digital converter circuit typically consists of four chief subcircuits:
The successive approximation register is initialized so that the most significant bit (MSB) is equal to a digital 1. This code is fed into the DAC, which then supplies the analog equivalent of this digital code (Vref/2) into the comparator circuit for comparison with the sampled input voltage. If this analog voltage exceeds Vin the comparator causes the SAR to reset this bit; otherwise, the bit is left a 1. Then the next bit is set to 1 and the same test is done, continuing this binary search until every bit in the SAR has been tested. The resulting code is the digital approximation of the sampled input voltage and is finally output by the SAR at the end of the conversion (EOC).
Mathematically, let Vin = xVref, so x in [−1, 1] is the normalized input voltage. The objective is to approximately digitize x to an accuracy of 1/2n. The algorithm proceeds as follows:
where, s(x) is the signum-function (sgn(x)) (+1 for x ≥ 0, −1 for x < 0). It follows using mathematical induction that |xn − x| ≤ 1/2n.
As shown in the above algorithm, a SAR ADC requires:
Example: The ten steps to converting an analog input to 10 bit digital, using successive approximation, is shown here, for all voltages from 5V to 0V in 0.1V iterations. Since the reference voltage is 5V, when the input voltage is also 5V all bits are set. As the voltage is decreased to 4.9V, only some of the least significant bits are cleared. The MSB will remain set until the input is one half the reference voltage, 2.5V.
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