Shockley-Queisser limit

In physics, the Shockley–Queisser limit or detailed balance limit or Shockley Queisser Efficiency Limit or SQ Limit refers to the maximum theoretical efficiency of a solar cell using a single p-n junction to collect power from the cell. It was first calculated by William Shockley and Hans-Joachim Queisser at Shockley Semiconductor in 1961. The limit is one of the most fundamental to solar energy production, and is considered to be one of the most important contributions in the field.

The limit places maximum solar conversion efficiency around 33.7% assuming a single p-n junction with a band gap of 1.34 eV (using an AM 1.5 solar spectrum). That is, of all the power contained in sunlight falling on an ideal solar cell (about 1000 W/m²), only 33.7% of that could ever be turned into electricity (337 W/m²). The most popular solar cell material, silicon, has a less favorable band gap of 1.1 eV, resulting in a maximum efficiency of about 32%. Modern commercial mono-crystalline solar cells produce about 24% conversion efficiency, the losses due largely to practical concerns like reflection off the front surface and light blockage from the thin wires on its surface.

The Shockley–Queisser limit only applies to cells with a single p-n junction; cells with multiple layers can outperform this limit. In the extreme, with an infinite number of layers, the corresponding limit is 86.8% using concentrated sunlight. (See Solar cell efficiency.)

In a traditional solid-state semiconductor such as silicon, a solar cell is made from two doped crystals, one an n-type semiconductor, which has extra free electrons, and the other a p-type semiconductor, which is lacking free electrons, referred to as "holes." When initially placed in contact with each other, some of the electrons in the n-type portion will flow into the p-type to "fill in" the missing electrons. Eventually enough will flow across the boundary to equalize the Fermi levels of the two materials. The result is a region at the interface, the p-n junction, where charge carriers are depleted on each side of the interface. In silicon, this transfer of electrons produces a potential barrier of about 0.6 V to 0.7 V.

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