Scalable Link Interface
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| Manufacturer | NVIDIA |
|---|---|
| Type | Multi-GPU |
| Release date | 2004 |
| Predecessor | Scan-Line Interleave |
Scalable Link Interface (SLI) is a brand name for a multi-GPU technology developed by NVIDIA for linking two or more video cards together to produce a single output. SLI is an algorithm of parallel processing for computer graphics, meant to increase the processing power available for graphics. The initialism SLI was first used by 3dfx for Scan-Line Interleave, which was introduced to the consumer market in 1998 and used in the Voodoo2 line of video cards. After buying out 3dfx, NVIDIA acquired the technology but did not use it. NVIDIA later reintroduced the SLI name in 2004 and intended for it to be used in modern computer systems based on the PCI Express (PCIe) bus; however, the technology behind the name SLI has changed dramatically.
SLI allows two, three, or four graphics processing units (GPUs) to share the workload when rendering real-time 3D computer graphics. Ideally, identical GPUs are installed on the motherboard that contains enough PCI-Express slots, set up in a master-slave configuration. All graphics cards are given an equal workload to render, but the final output of each card is sent to the master card via a connector called the SLI Bridge. An example, in a two graphics card setup, the master works on the top half of the scene, the slave the bottom half. Once the slave is done, it sends its render to the master to combine into one image before sending it to the monitor.
The SLI bridge is used to reduce bandwidth constraints and send data between both graphics cards directly. It is possible to run SLI without using the bridge connector on a pair of low-end to mid-range graphics cards (e.g. 7100GS or 6600GT) with NVIDIA's Forceware drivers 80.XX or later. Since these graphics cards do not use as much bandwidth, data can be relayed through just the chipsets on the motherboard. However, if there are two high-end graphics cards installed and the SLI bridge is omitted, the performance will suffer severely as the chipset does not have enough bandwidth.
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