RapidIO
RapidIO - the unified fabric for Performance Critical Computing
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| Year created | 2000 |
|---|---|
| Width in bits | Port widths of 1, 2, 4, 8, and 16 lanes |
| No. of devices | Sizes of 256, 65,536, and 4,294,967,296 |
| Speed |
Per lane (each direction): |
| Style | Serial |
| Hotplugging interface | Yes |
| External interface | Yes, Chip-Chip, Board-Board (Backplane), Chassis-Chassis |
Per lane (each direction):
The RapidIO architecture is a high-performance packet-switched, interconnect technology. RapidIO supports messaging, read/write and cache coherency semantics. RapidIO fabrics guarantee in-order packet delivery, enabling power- and area- efficient protocol implementation in hardware. Based on industry-standard electrical specifications such as those for Ethernet, RapidIO can be used as a chip-to-chip, board-to-board, and chassis-to-chassis interconnect. The protocol is marketed as: RapidIO - the unified fabric for Performance Critical Computing, and is used in many applications such as Data Center & HPC, Communications Infrastructure, Industrial Automation and Military & Aerospace that are constrained by at least one of size, weight, and power (SWaP).
RapidIO has its roots in energy-efficient, high-performance computing. The protocol was originally designed by Mercury Computer Systems and Motorola (Freescale) as a replacement for Mercury's RACEway proprietary bus and Freescale's PowerPC bus. The RapidIO Trade Association was formed in February 2000, and included telecommunications and storage OEMs as well as FPGA, processor, and switch companies. The protocol was designed to meet the following objectives:
The RapidIO Specification Revision 1.1, released in 2001, defined a wide, parallel bus. This specification did not achieve extensive commercial adoption.
The RapidIO Specification Revision 1.2, released in 2002, defined a serial interconnect based on the XAUI physical layer. Devices based on this specification achieved significant commercial success within wireless baseband, imaging and military compute.
The RapidIO Specification Revision 2.0, released in 2008, added more port widths (2×, 8×, and 16×) and increased the maximum lane speed to 6.25 GBd / 5 Gbit/s. Revision 2.1 has repeated and expanded the commercial success of the 1.2 specification.
The RapidIO Specification Revision 3.0, released in 2013, has the following changes and improvements compared to the 2.x specifications:
The RapidIO Specification Revision 4.0 was released in 2016. has the following changes and improvements compared to the 3.x specifications:
RapidIO fabrics enjoy dominant market share in global deployment of cellular infrastructure 3G, 4G & LTE networks with millions of RapidIO ports shipped into wireless base stations worldwide. RapidIO fabrics were originally designed to support connecting different types of processors from different manufacturers together in a single system. This flexibility has driven the widespread use of RapidIO in wireless infrastructure equipment where there is a need to combine heterogeneous, DSP, FPGA and communication processors together in a tightly coupled system with low latency and high reliability.
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