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Radeon R400

ATi Radeon X700/X800 Series
ATI Logo
Release date 2004-2005
Codename Loki
Cards
Entry-level None
Mid-range X700, X740
High-end X800
Enthusiast X850
API support
Direct3D Direct3D 9.0b
Shader Model 2.0b
OpenGL OpenGL 2.0
History
Predecessor Radeon 9000 Series
Radeon X300 Series
Radeon X500 Series
Radeon X600 Series
Successor Radeon X1000 Series

The R420 GPU, developed by ATI Technologies, was the company's basis for its 3rd-generation DirectX 9.0/OpenGL 2.0-capable graphics cards. Used first on the Radeon X800, the R420 was produced on a 0.13 micrometer (130 nm) low-K photolithography process and used GDDR-3 memory. The chip was designed for AGP graphics cards.

Driver support of this core was discontinued as of Catalyst 9.4, and as a result there is no official Windows 7 support for any of the X700 - X850 products.

In terms of supported DirectX features, R420 (codenamed Loki) was very similar to the R300. R420 basically takes a "wider is better" approach to the previous architecture, with some small tweaks thrown in to enhance it in various ways. The chip came equipped with over double the pixel and vertex pushing resources compared to the Radeon 9800 XT's R360 (a minor evolution of the R350), with 16 DirectX 9.0b pixel pipelines and 16 ROPs. One would not be far off seeing the X800 XT basically as a pair of Radeon 9800 cores connected together and also running with a ~30% higher clock speed.

The R420 design was a 4 "quad" arrangement (4 pipelines per quad.) This organization internally allowed ATI to disable defective "quads" and sell chips with 12, 8 or even 4 pixel pipelines, an evolution of the technique used with Radeon 9500/9700 and 9800SE/9800. The separation into "quads" also allowed ATI to design a system to optimize the efficiency of the overall chip. Coined the "quad dispatch system", the screen is tiled and work is spread out evenly among the separate "quads" to optimize their throughput. This is how the R300-series chips performed their tasks as well, but R420 refined this by allowing programmable tile sizes in order to control work flow on a finer level of granularity. Apparently by reducing tile sizes, ATI was able to optimize for different triangle sizes.


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Wikipedia

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