R3000A

The R3000 is a full 32 bit RISC microprocessor chipset developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor. It operated at 20, 25 and 33.33 MHz.

The MIPS 1 instruction set is very small compared to the instruction sets of other microprocessors, such as the contemporary 80x86, 680x0 architectures), as it includes only most commonly used instructions and supports very limited number of addressing modes. The small number of CPU instructions, as well as other instruction set features—fixed instruction length and only three different types of instruction formats—greatly simplify instruction decoding and processing. To speed up processing even further the CPU employs a 5-stage instruction pipeline. The pipeline design allows the R3000 CPU to execute most instructions at a rate close to 1 instruction per cycle.

The MIPS architecture supports up to four coprocessors. In addition to the CPU core, the R3000 microprocessor includes a Control Processor (CP), which contains a Translation Lookaside Buffer and a Memory Management Unit. The CP works as a coprocessor. Besides the CP, the R3000 can also support an external R3010 numeric coprocessor and two other external coprocessors.

The R3000 CPU does not include its own level 1 cache. Instead, the processor has an on-chip cache controller which controls separate external data and instruction caches. The size of each external cache can be as large as 256 KB. The CPU can access both caches during the same CPU cycle.

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