R10000

The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture (ISA) developed by MIPS Technologies, Inc. (MTI), then a division of Silicon Graphics, Inc. (SGI). The chief designers were Chris Rowen and Kenneth C. Yeager. The R10000 microarchitecture was known as ANDES, an abbreviation for Architecture with Non-sequential Dynamic Execution Scheduling. The R10000 largely replaced the R8000 in the high-end and the R4400 elsewhere. MTI was a fabless semiconductor company, the R10000 was fabricated by NEC and Toshiba. Previous fabricators of MIPS microprocessors such as Integrated Device Technology (IDT) and three others did not fabricate the R10000 as it was more expensive to do so than the R4000 and R4400.

The R10000 was introduced in January 1996 at clock frequencies of 175 MHz and 195 MHz. A 150 MHz version was introduced in the O2 product line in 1997, but discontinued shortly after due to customer preference for the 175 MHz version. The R10000 was not available in large volumes until later in the year due to fabrication problems at MIPS's foundries. The 195 MHz version was in short supply throughout 1996, and was priced at US$3,000 as a result.

On 25 September 1996, SGI announced that R10000s fabricated by NEC between March and the end of July that year were faulty, drawing too much current and causing systems to shut down during operation. SGI recalled 10,000 R10000s that had shipped in systems as a result, which impacted the company's earnings.

In 1997, a version of R10000 fabricated in a 0.25 µm process enabled the microprocessor to reach 250 MHz.

Users of the R10000 included:

The R10000 is a four-way superscalar design that implements register renaming and executes instructions out-of-order. Its design was a departure from previous MTI microprocessors such as the R4000, which was a much simpler scalar in-order design that relied largely on high clock rates for performance.

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