In digital logic design, quasi delay-insensitive (QDI) or speed independent (SI) circuits are the most robust class of asynchronous circuit that are still turing-complete. While delay-insensitive circuits make no assumptions regarding the delay of wires or gates and are not Turing-complete, QDI circuits make the weakest delay assumption necessary to be so, the isochronic fork.
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QDI circuits have been used to manufacture a large number of research chips, a small selection of which follows.
A QDI circuit is a system of events which are organized as a network of interacting cycles. In this system, a gate is mapped to two events in which it's output node is driven either from GND to Vdd by the pull up network or from Vdd to GND by the pull down network. Furthermore, these two events must belong to the same cycles and every cycle must have an odd number of gates. The simplest example, a ring oscillator, consists of exactly one cycle of three gates (six events).
Two cycles may interact using a c-element which waits for it's inputs to match before copying the value to it's output. This effectively forces the two cycles to synchronize at the c-element. Connecting three or more of these cycles in a line creates a pipeline allowing the cycles to trigger one after another like dominos.
This representation makes it relatively easy to understand small systems, but quickly becomes too much to manage as systems get larger. So, larger systems are partitioned into modules called processes which describe the interaction between a set of cycles. A process boundary cuts all of the participating cycles which then act as channel ports each with two circuit nodes called the request and acknowledge. The process that drives the request is the sender while the process that drives the acknowledgement is the receiver. Now, the sender and receiver communicate using certain and the sequential triggering of communication actions from one process to the next is referred to as a token that traverses the pipeline.