Positive emitter-coupled logic

In electronics, emitter-coupled logic (ECL) is a high-speed integrated circuit bipolar transistor logic family. ECL uses an overdriven BJT differential amplifier with single-ended input and limited emitter current to avoid the saturated (fully on) region of operation and its slow turn-off behavior. As the current is steered between two legs of an emitter-coupled pair, ECL is sometimes called current-steering logic (CSL),current-mode logic (CML) or current-switch emitter-follower (CSEF) logic.

In ECL, the transistors are never in saturation, the input/output voltages have a small swing (0.8 V), the input impedance is high and the output resistance is low; as a result, the transistors change states quickly, gate delays are low, and the fanout capability is high. In addition, the essentially-constant current draw of the differential amplifiers minimises delays and glitches due to supply-line inductance and capacitance, and the complementary outputs decrease the propagation time of the whole circuit by reducing inverter count.

ECL's major disadvantage is that each gate continuously draws current, which means it requires (and dissipates) significantly more power than those of other logic families, especially when quiescent.

The equivalent of emitter-coupled logic made out of FETs is called source-coupled logic (SCFL).

A variation of ECL in which all signal paths and gate inputs are differential is known as differential current switch (DCS) logic.

ECL was invented in August 1956 at IBM by Hannon S. Yourke. Originally called current-steering logic, it was used in the Stretch, IBM 7090, and IBM 7094 computers. The logic was also called a current mode circuit. It was also used to make the ASLT circuits in the IBM 360/91.

Yourke's current switch was a differential amplifier whose input logic levels were different from the output logic levels. "In current mode operation, however, the output signal consists of voltage levels which vary about a reference level different from the input reference level." In Yourke's design, the two logic reference levels differed by 3 volts. Consequently, two complementary versions were used: an NPN version and a PNP version. The NPN output could drive PNP inputs, and vice versa. "The disadvantages are that more different power supply voltages are needed, and both pnp and npn transistors are required."

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