Physical Address Extension
In computing, Physical Address Extension (PAE), sometimes referred to as Page Address Extension, is a memory management feature for the IA-32 architecture. PAE was first introduced in the Pentium Pro. It defines a page table hierarchy of three levels, with table entries of 64 bits each instead of 32, allowing these CPUs to access a physical address space larger than 4 gigabytes (232 bytes).
The page table structure used by x86-64 CPUs when operating in 64-bit mode further extends the page table hierarchy to four levels, extending the virtual address space, and uses additional physical address bits at all levels of the page table, extending the physical address space. It also uses the topmost bit of the 64-bit page table entry as an NX bit.
PAE was first implemented in the Intel Pentium Pro in 1995, although the accompanying chipsets usually lacked support for the required extra address bits.
PAE is supported by Intel Pentium Pro and later Pentium-series processors. The first Pentium M family processors ("Banias") also support PAE; however, they do not show the PAE support flag in their CPUID information. It was also available on AMD processors including the AMD Athlon (although the chipsets for are limited to 32-bit addressing) and later AMD processor models.
When AMD defined their AMD64 architecture as an extension of x86, they defined an enhanced version of PAE to be used while the processor was in 64-bit mode ("long mode"). It supports up to 48-bit virtual addresses, 52-bit physical addresses, and includes NX bit functionality. This version of PAE is the mandatory memory paging model in long mode on x86-64 processors; there is no "non-PAE mode" while in long mode. The documentation for "Intel 64", the Intel version of x86-64, refers to these page table formats as "IA-32e paging" rather than "PAE".
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