PCI Express 2.0

PCI Express

Year created	2004; 13 years ago (2004)
Created by	Intel Dell HP IBM
Supersedes	AGP PCI PCI-X
Width in bits	1–32
No. of devices	One device each on each endpoint of each connection. PCI Express switches can create multiple endpoints out of one endpoint to allow sharing one endpoint with multiple devices.
Speed	For single-lane (×1) and 16-lane (×16) links, in each direction: v. 1.x (2.5 GT/s): 250 MB/s (×1) 4 GB/s (×16) v. 2.x (5 GT/s): 500 MB/s (×1) 8 GB/s (×16) v. 3.x (8 GT/s): 985 MB/s (×1) 15.75 GB/s (×16) v. 4.0 (16 GT/s): 1.969 GB/s (×1) 31.51 GB/s (×16)
Style	Serial
Hotplugging interface	Yes, if ExpressCard, Mobile PCI Express Module, XQD card or Thunderbolt
External interface	Yes, with PCI Express External Cabling, such as Thunderbolt

PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X, and AGP bus standards. PCIe has numerous improvements over the older standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, a more detailed error detection and reporting mechanism (Advanced Error Reporting, AER), and native hot-plug functionality. More recent revisions of the PCIe standard provide hardware support for I/O virtualization.

The PCI Express electrical interface is also used in a variety of other standards, most notably in ExpressCard as a laptop expansion card interface, and in SATA Express as a computer storage interface.

Format specifications are maintained and developed by the PCI-SIG (PCI Special Interest Group), a group of more than 900 companies that also maintain the conventional PCI specifications. PCIe 3.0 is the latest standard for expansion cards that are in production and available on mainstream personal computers.

Conceptually, the PCI Express bus is a high-speed serial replacement of the older PCI/PCI-X bus. One of the key differences between the PCI Express bus and the older PCI is the bus topology; PCI uses a shared parallel bus architecture, in which the PCI host and all devices share a common set of address, data and control lines. In contrast, PCI Express is based on point-to-point topology, with separate serial links connecting every device to the root complex (host). Due to its shared bus topology, access to the older PCI bus is arbitrated (in the case of multiple masters), and limited to one master at a time, in a single direction. Furthermore, the older PCI clocking scheme limits the bus clock to the slowest peripheral on the bus (regardless of the devices involved in the bus transaction). In contrast, a PCI Express bus link supports full-duplex communication between any two endpoints, with no inherent limitation on concurrent access across multiple endpoints.

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