OpenRISC
| Designer | Damjan Lampret, with contributions from others in the OpenRISC community |
|---|---|
| Bits | 32-bit, 64-bit |
| Design | RISC |
| Encoding | Fixed |
| Open | Yes |
| Registers | |
| General purpose | 16 or 32 |
| Floating point | Optional |
OpenRISC is a project to develop a series of open source instruction set architectures based on established reduced instruction set computing (RISC) principles. It is the original flagship project of the OpenCores community.
The first (and currently only) architectural description is for the OpenRISC 1000, describing a family of 32 and 64-bit processors with optional floating point and vector processing support, and the OpenRISC 1200 implementation of this was designed by Damjan Lampret in 2000, written in the Verilog hardware description language.
The hardware design was released under the GNU Lesser General Public License (LGPL), while the models and firmware were released under the GNU General Public License (GPL).
A reference SoC implementation based on the OpenRISC 1200 was developed, known as ORPSoC (the OpenRISC Reference Platform System-on-Chip). A number of groups have demonstrated ORPSoC and other OR1200 based designs running on FPGAs, and there have been a number of commercial derivatives produced.
OpenCores has always been a commercially owned organization. In 2015, the core active users of OpenCores established the independent Free and Open Source Silicon Foundation (FOSSi), and registered the libreCores.org website, as the basis for all future development, independent of commercial control.
The instruction set is a reasonably simple MIPS-like traditional RISC using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32 and 64 bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout. The OpenRISC specification includes all features common to modern desktop/server processors: a supervisor mode and virtual memory system, optional read, write and execute control for memory pages, and instructions for synchronization and interrupt handling between multiple processors.
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