Motorola 68060

The Motorola 68060 ("sixty-eight-oh-sixty") is a 32-bit microprocessor from Motorola released in 1994. It is the successor to the Motorola 68040 and is the highest performing member of the 68000 series. Two derivatives were produced, the 68LC060 and the 68EC060.

There is an LC (Low-Cost) version, without an FPU and EC (Embedded Controller), without MMU and FPU. The 68060 design was led by Joe Circello.

The 68060 shares most architectural features with the P5 Pentium. Both have a very similar superscalar in-order dual instruction pipeline configuration, and an instruction decoder which breaks down complex instructions into simpler ones before execution. However, a significant difference is that the 68060 FPU is not pipelined and is therefore up to three times slower than the Pentium in floating point applications. In contrast to that, integer multiplications and bit shifting instructions are significantly faster on the 68060. An interesting feature of the 68060 is the ability to execute simple instructions in the address generation unit (AGU) and thereby supply the result two cycles before the ALU. Another point of interest is that large amounts of commercial compiled code were analyzed for clues as to which instructions would be the best candidates for performance optimization.

Against the Pentium, the 68060 could perform better on mixed code; Pentium's decoder could not issue an FP instruction every opportunity and hence the FPU was not superscalar as the ALUs were. If the 68060's non-pipelined FPU could accept an instruction, it could be issued one by the decoder. This meant that optimizing for the 68060 was easier: no rules prevented FP instructions from being issued whenever was convenient for the programmer other than well understood instruction latencies. However, with properly optimized and scheduled code, the Pentium's FPU was capable of double the clock for clock throughput of the 68060's FPU.

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